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ESDA18-1F2
TransilTM, transient voltage suppressor
Features

Stand-off voltage 16V Unidirectional device Low clamping factor VCL/VBR Fast response time Very thin package: 0.65 mm
Flip Chip (4 bumps)
Complies with the following standards
IEC 61000-4-2 Level 4 - 15 kV (air discharge) - 8 kV (contact discharge)
Figure 1.
Pin configuration (bump side)
Description
A
The ESDA18-1F2 is a single line Transil diode designed specifically for the protection of integrated circuits into portable equipment and miniaturized electronics devices subject to ESD and EOS transient overvoltages.
K
B 1
A
2
K A
K
A
TM: Transil is a trademark of STMicroelectronics.
April 2008
Rev 2
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www.st.com 8
Characteristics
ESDA18-1F2
1
Characteristics
Table 1.
Symbol
Absolute ratings (limiting value, per diode)
Parameter and test conditions Peak pulse power dissipation 10 / 1000 s pulse Value 100 Tj initial = Tamb 700 tp=10 ms Tj initial = Tamb 8 125 - 65 to + 175 A C C W Unit
PPP
Peak pulse power dissipation 8 / 20 s pulse Non repetitive surge peak forward current Maximum operating junction temperature Storage temperature range
IFSM Tj Tstg
Table 2.
Symbol VBR IRM VRM VCL Rd IPP C
Electrical characteristics (Tamb = 25 C)
Parameter Breakdown voltage Leakage current Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Capacitance VBR IRM IR min. max. max. max. IF = 850 mA V V 18 mA 1 A 0.5 V 10 V 20 A 1 V 1.3 10-4/C 8.5 VR=0 V pF 230 VRM VCL IPP (1) VF (2) max. T max. C typ.
Slope: 1/Rd IPP VF VCL VBR VRM IRM V IF I
Order number
ESDA18-1F2
16
1. 8 / 20 s pulse waveform. 2. A DC current is not recommended for more than 5 sec. Even if Transil failure mode is short circuit the bumps could exceed melting temperature and the component disassembled from the board.
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ESDA18-1F2
Characteristics
Figure 2.
Relative variation of peak pulse power versus initial junction temperature
Figure 3.
Peak pulse power versus exponential pulse duration
PPP[Tj initial] / PPP[Tj initial=25C)
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150 100 1000 10000
PPP(W)
Tj initial=25C
Tj(C)
10 1 10
tp(s)
100 1000
Figure 4.
Clamping voltage versus peak pulse current (typical values, exponential waveform)
Figure 5.
Forward voltage drop versus peak forward current (typical values)
IFM(A)
IPP(A)
100.0
8/20s Tj initial=25C
1.E+01
1.E+00 10.0
Tj=125C
Tj=25C
1.E-01 1.0 1.E-02
VCL(V)
0.1 10 12 14 16 18 20 22 24 26 28 30 1.E-03 0.0 0.2 0.4 0.6 0.8
VFM(V)
1.0 1.2 1.4 1.6 1.8 2.0
Figure 6.
Junction capacitance versus reverse voltage applied (typical values)
Figure 7.
Relative variation of leakage current versus junction temperature (typical values)
C(pF)
300
F=1MHz VOSC=30mVRMS Tj=25C
IR[Tj] / IR[Tj=25C]
100
VR=10V
250
200
150
10
100
50
VR(V)
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 25 50
Tj(C)
75 100 125
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Application information
ESDA18-1F2
2
Application information
One major point is that the ESDA18-1F2 has to ensure the safety during reverse battery operation. Indeed, during this operation the device must clamp the DC reverse voltage below 1.3 V @ 0.85 A (max current). Thus reverse battery operation has been simulated by inverting the polatrity of the Transil (please see figures 8 and 9) Figure 8. Reverse battery operation setup
Equivalent mobile phone impedance PTC Vmains I V 4.7 k 1 nF
ESDA18-1F2
Figure 9.
Reverse battery operation results
A short calculation based on Reverse battery operation results figures clearly show that in such real phone application the ESDA18-1F2 clamp the DC voltage below 1.3 V. Typically the ESDA18-1F2 can clamp the DC voltage @ 0.9 V @ 0.76 A DC current:
2 x V max 2 x 1.4 V DC = ---------------------- ----------------- 0.9V 3.14 2 x I max 2 x 1.2 I DC = -------------------- ----------------- 0.76A 3.14
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ESDA18-1F2
Ordering information scheme
3
Ordering information scheme
Figure 10. Ordering information scheme
ESDA
ESD Array Breakdown Voltage 18 = 18 Volts max. Number of line 1 = signle line Package F = Flip Chip x = 2: Lead-free, pitch = 500 m, bump = 315 m
18 - 1
Fx
4
Packing information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 11. Flip Chip package dimensions
500 m 50 650 m 65 315 m 50
225 m 0.92 mm 30 m
225 m
0.92 mm 30 m
500 m 50
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Packing information
ESDA18-1F2
Figure 12. Footprint recommendations
Figure 13. Marking
Copper pad Diameter: 250 m recommended, 300m max
Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)
E
Solder stencil opening: 330 m
Solder mask opening recommendation: 340 m min for 315 m copper pad diameter
xxz y ww
Figure 14. Flip Chip tape and reel specification
Dot identifying Pin A1 location 4 0.1 O 1.5 0.1
1.75 0.1 3.5 0.1
1.0
0.73 0.05
All dimensions in mm
8 0.3
STE
STE
STE
1.0
xxx yww
xxx yww
xxx yww
4 0.1
User direction of unreeling
Note:
More packing information is available in the application notes: AN1235: "Flip Chip: Package description and recommendations for use" AN1751: "EMI Filters: Recommendations and measurements"
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ESDA18-1F2
Ordering information
5
Ordering information
Table 3. Ordering Information
Marking EE Package Flip Chip Weight 1.25 mg Base qty 5000 Delivery mode Tape and reel 7"
Order code ESDA18-1F2
6
Revision history
Table 4.
Date 09-May-2005 18-Apr-2008
Document revision history
Revision 1 2 First issue. Updated ECOPACK statement. Updated Figure 11, Figure 13, and Figure 14. Reformatted to current standards. Changes
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ESDA18-1F2
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